Engineer would be minimum 8+ years of experience and capable of leading a DFT engineers team with at least 3 years of Lead experience. Responsibilities ● Good DFT fundamentals – Scan, ATPG, MBIST, LBIST, SSN etc. ● Good at Scan and ATPG. Understanding of MBIST and pattern simulations will be a plus ● Experience in Tessent DFT tools a MUST ● Expertise in coverage improvement techniques ● Experience in -…

PTPX Experience – 3 to8 yrs

Lower Nodes, Finfet Technologies Experience – 6+ Yrs

The selected engineer will be working with multiple teams in implementing new features and developing new IPs for multiple variants of RISCV based SoCs. The engineers should be able to communicate effortlessly with different stakeholders in the project and should be handling the deliverables as per the quality standards meeting the schedule. Responsibilities ● Excellent understanding of SoC Architecture, Bus Structures, Peripherals etc ● Familiarity with ARM based SoCs will…

Well versed with the timing closure (STA), timing closure methodologies Pre/Post-layout constraint development to timing closure Handshake with the design team and develop functional/DFT constraints Experience – 8+yrs

Proficient in SoC verification writing ‘C’ test cases for SoC DV Experience – 8+yrs

Exp in Perl scripting, Exp in Lint, CDC, UPF, constraints Experience – 8+ yrs