Fusion Compiler Experience – 3 to 5yrs

Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure. Responsibilities ● Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM. ● Must have participated in all stages of the design (floor planning, placement, CTS,…

Experience on Networking protocol Experience – 7+yrs

The core skill set expected from the team is: Exceptional Digital fundamentals Hands on experience in System Design with FPGA devices with relevant FPGA EDA tools Experience in designing and implementing FPGA based solutions in Microchip or Xilinx or Altera FPGAs Write high quality code in Verilog/System Verilog, VHDL and C code for embedded processors. Maintain existing code. Developing testbenches using Verilog/System Verilog and verifying validation designs in simulation environment…

Proficient in SV/ UVM based IP verification Must have good debugging skills Experience – 7+ Yrs

Coding, validation, Verilog, C Experience – 8 to 12yrs

HAPS, Veloce, palladium, Design, FPGA Experience – 5+ Yrs