Coding, validation, Verilog, C Experience - 8 to 12yrs

HAPS, Veloce, palladium, Design, FPGA Experience - 5+ Yrs

Engineer would be minimum 8+ years of experience and capable of leading a DFT engineers team with at least 3 years of Lead experience. Responsibilities ● Good DFT fundamentals - Scan, ATPG, MBIST, LBIST, SSN etc. ● Good at Scan and ATPG. Understanding of MBIST and pattern simulations will be a plus ● Experience in Tessent DFT tools a MUST ● Expertise in coverage improvement techniques ● Experience in -…

PTPX Experience - 3 to8 yrs

Lower Nodes, Finfet Technologies Experience - 6+ Yrs